Soluções inovadoras em hardware reconfigurável para processamento online em um detector com alta taxa de eventos

Abstract

The Large Hadron Collider (LHC) at CERN, the world's largest operational particle accelerator, will undergo an upgrade to the HL-LHC (High Luminosity LHC) phase, increasing the luminosity and energy of proton-proton collisions. For the ATLAS experiment, the accelerator upgrade process impacts, among other things, the energy measurement system (calorimeter) and the event selection and data acquisition system (Trigger and Data Acquisition - TDAQ). The changes proposed by this upgrade process may cause the superposition of signals measured by the TileCal sensors, affecting the particle characterization process. To mitigate the effects caused by signal distortion, it becomes necessary to perform the estimation of the original signal in an online manner. Another challenge for the HL-LHC operation is the new hardware component, the Global Trigger. It will implement the computing and selection algorithms, and one of these algorithms is the NeuralRinger, a method that combines a ring-shaped representation of electromagnetic showers and machine learning to efficiently select electrons. In this context, the main objective of this work is to develop online processing solutions in FPGA for the problems generated for the ATLAS experiment due to the LHC operation scenario in HL-LHC. This work proposes a hardware solution for energy estimation and also the implementation of the NeuralRinger in the Global Trigger. For energy estimation, two different techniques were implemented and evaluated: one based on the FIR filter, and the other on the Positive Gradient Descent algorithm. The NeuralRinger was designed and implemented as a component integrated into the Global Event Processor (GEP), which is the core of the Global Trigger. The error results from the implementations of the energy estimation and electron selection algorithms indicated the efficiency of the hardware implementation. The implemented circuits were also synthesized for the FPGAs defined in the ATLAS electronics upgrade project: the Xilinx XC7VX485T for the TileCal electronics, used in the design of the energy estimation algorithms, and the Xilinx Virtex UltraScale+ VCU118 for the Global Trigger, used in the NeuralRinger design. The circuit synthesis results for energy estimation, using the deterministic approach, reported a utilization of approximately 0.8% of Registers, LUTs, and DSPs, and, for the iterative approach, approximately 11% for LUTs, 9% for Registers, and 17% for DSPs. For the NeuralRinger, the synthesis tool reported a utilization of 1.42% of LookUp Tables and 0.96% of Flip-Flops for the ring construction circuit, and 0.12% of LookUp Tables and 0.26% of Flip-Flops for the neural network. These results indicated the viability of deploying both solutions on the respective FPGAs boards.